With high bandwidth applications (e.g., full band cable and satellite receivers, serial links and short range wireless communications) becoming more and more popular, there is increasing demand for high speed and high-performance analog-to-digital convertors (ADCs). An effective way to improve the throughput of an ADC is to place several ADCs that operate at a fraction of the total sample rate of the ADC in a time-interleaved architecture. However, it is a challenge to control and compensate mismatch (e.g., offset, gain, and timing) of the channel ADCs with the time-interleaved architecture.